Oscillators produce a steady and stable, periodic time-varying output waveform which can serve as the information or timing signal for the signal-processing circuits. Early clock oscillators were developed using a series of odd inverter stages configured in a loop or a ring. Due to the inverters being single ended devices, they tended to have poor common mode rejection and swung from rail to rail and therefore the control of the frequency in such clock oscillators was difficult to achieve.
Quartz crystal oscillators were introduced in order to achieve a nearly constant oscillation frequency. These quartz oscillators required external components to an integrated circuit such as the quartz crystal and one or more capacitors placed on the printed circuit board. While a quartz crystal oscillator can generate an accurate constant frequency, multiple crystals of various frequencies must be combined to achieve multiple frequencies within a single circuit. In order to conserve space and decrease component count, it is desirable to generate multiple frequencies from a single oscillating source without multiple or external components.
Frequency synthesizers were introduced in order to achieve a desired range of frequencies and also minimize the required component count. Of present interest is a variable frequency oscillator circuit having a phase locked loop (PLL) with a voltage controlled oscillator (VCO) to properly maintain a desired frequency. An example of a PLL clock generator circuit is taught by Ian A. Young, Jeffrey K. Greason, and Keng I. Wong in "A PLL Clock Generator with 5 to 110 MHZ of Lock Range for Microprocessors." IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, Nov. 1992. A charge pump and loop filter are used to generate a control voltage to either increase or decrease the frequency of the VCO, as illustrated in FIG. 2 of the Young et al. article. The VCO is then followed by a divide-by-2 circuit for generating an accurate 50% duty cycle clock waveform.
The VCO taught by Young et al. is based on a five stage ring oscillator. Each stage of this VCO is a current-controlled differential delay cell which includes a pair of source-coupled voltage-controlled resistors as load elements. This circuit utilizes a replica biasing cell to control both the current in each stage and the voltage controlled resistors. The control voltage is converted to a current signal and then applied to each of the five stages to achieve the desired frequency. A reference voltage and a control signal are used by the replica biasing cell to control the voltage-controlled resistors and hold the signal amplitude constant.
The clock generator taught by Young et al. is sensitive to common mode noise at the output VCR of the operational amplifier as illustrated in FIG. 2 of the Young et al. article. The output voltage VCR is used as the control voltage to control the variable resistors Rvcr. Any distortion or noise in the control voltage VCR will change the time constant of the delay stages to effect the frequency and period of the VCO.
When a high frequency output is desired, using the Young et al. clock generator, there are also problems associated with the gain margin. To obtain a high frequency oscillation, fewer stages in the oscillator and a small time constant (.tau.=RC) are desired. To obtain oscillation for an inverter chain, a 180 degree phase shift and a voltage gain greater than one must be achieved. To obtain the proper phase margin, additional stages of the inverter are required for the inverter chain. To obtain the proper gain margin, either the gain of each inverter stage must be large or additional cascaded inverter stages are required. The capacitance value C, used to calculate the time constant, is dominated by the gate capacitance of the input transistors. The resistance value R, used to calculate the time constant, is equivalent to the variable resistance value Rvcr. The DC voltage gain Av of each delay stage is proportional to the value Rvcr*gm, where the value gm is equal to the transconductance of the input gate, which is proportional to the size of the transistor. For a fixed, minimum length L of the transistor, the DC voltage gain Av is proportional to the time constant value, Rvcr*C. Because the gain is proportional to the time constant value in the Young et al. clock generator circuit, the requirement of high gain and a small time constant are difficult to meet at the same time.
The jitter of an oscillator is a quantity used to express the quality of the oscillator's output signal. An output signal waveform has no jitter if its period is constant and does not vary over time. If an oscillator's output signal waveform has jitter, its period will vary over time and the edges or transition points of the waveform will correspondingly vary over time.
Another quantity of concern when discussing PLL oscillators is the power supply rejection ratio or how well the circuit rejects noise which is inherent to the power supply. Power supply noise comes from cycle-to-cycle switching of large-capacitance nodes within the chip and a second component which comes from the variation of circuit activity within the chip. This power supply noise can directly change the output frequency and phase of the oscillator. For example, if the power supply noise is large enough and occurs near a transition point, the output signal can contain spurious transition points caused by this noise from the power supply. Therefore it is very important that an oscillator have a high power supply rejection ratio (PSRR) in order to preserve the desired output waveform and reduce the effects of power supply noise.
A complementary metal oxide semiconductor (CMOS) linear comparator of the prior art is illustrated in FIG. 1A. The transistor 110 is an N-type field effect transistor (NFET) and includes a gate 120 which is coupled to the input INP. The gate 121 of the NFET 111 is coupled to the input INN. The output voltage level VOUT, which is measured between the node OUTP 101 and ground, is generated in response to the polarity of the voltage difference VIN between the two inputs INP and INN. The current I which flows through the current source 115 into the negative voltage supply VN 103 is a constant. The load transistors 112 and 113 are connected to the positive supply voltage VP 102.
A second comparator of the prior art which is nonlinear is illustrated in FIG. 1B. The transistors 110 and 111 are NFETs and the gates of each of the transistors 110 and 111 are coupled to the differential input VIN. The source of the transistor 110 is coupled to the source of the transistor 111 and to the current source 115. The drain of the transistor 110 is coupled to the drain of the transistor 130, to the gate of the transistor 131, and to the gate and drain of the transistor 133. The drain of the transistor 111 is coupled to the drain of the transistor 131, to the gate of the transistor 130, and to the gate and drain of the transistor 132. The sources of the transistors 130, 131, 132 and 133 are all coupled to the positive power supply voltage VP. The differential output voltage VOUT, which is measured between the drains of the transistors 130 and 131 is generated in response to the polarity of the input voltage difference VIN. The current I which flows through the current source 115 is a constant.
The cross-coupling of the gates of the transistors 130 and 131 in the comparator of FIG. 1B adds hysteresis characteristics to the circuit. Hysteresis is used to combat noise which is introduced to the circuit. Hysteresis is the quality of the comparator in which the input threshold changes as a function of the input or output level. Specifically, when the input level passes the first threshold or trip point, the output changes and the input threshold or trip point is subsequently reduced so that the input must return beyond the first threshold before the comparator's output will change states again.
As an example, consider that the gate 121 of the transistor 111 is tied to ground and the gate 120 of the transistor 110 is much greater than zero volts, causing the transistor 110 to turn on and the transistor 111 to turn off, thus turning on the transistors 131 and 133 and turning off the transistors 130 and 132. The current I will flow through the transistors 110, 130 and 133, causing the positive side OUTP of the output voltage VOUT to be at a high voltage level. Assume the input voltage INP changes direction, i.e. from a positive level towards a negative level, as the input voltage VIN decreases toward the threshold or trip point, the current through the transistor 110 decreases and some of the tail current I begins to flow through the transistor 111. This will continue until the point where the current through the transistor 111 equals the current through the transistor 131. Just beyond this point, the comparator output VOUT switches states so that the positive side of the output voltage VOUT is at a low voltage level. Once the threshold is reached and the comparator output changes state, the majority of the tail current I will flow through the transistors 111, 131 and 132 and the transistor 130 turns on and the transistors 110, 131, and 133 are turned off. Assuming the input voltage changes direction once again, the input voltage starts to increase above zero volts, the circuit reaches a point at which the current in the transistor 110 increases until it equals the current in the transistor 130. The input voltage at this point is the second threshold or trip point.
A disadvantage to the comparators of FIGS. 1A and 1B is that on a transition point, the output voltage swings close to the range from rail to rail, or from the positive supply voltage VP to the negative supply voltage VN. Therefore, the frequency of these comparators is directly limited by the time that it takes the circuit to switch from one power supply voltage level to the other power supply voltage level. When the output voltage is nearly at the negative supply voltage VN level, it takes the comparator time to recover and swing the output voltage close to the positive power supply voltage VP level on a transition point.
What is needed is an improved comparator or differential amplifier, which has improved jitter and power supply rejection ratio characteristics. What is further needed is an improved differential amplifier or variable delay cell for use in an oscillator which reduces or eliminates start up problems associated with oscillators of the prior art. What is also needed is an oscillator with an improved frequency response because its output voltage does not have to swing from rail to rail. What is also needed is a VCO having a reduced number of stages in order to provide a higher maximum frequency of oscillation and a larger frequency range.